In a processor that executes a program using virtual memory, a memory management unit (hereinafter referred to as an MMU) performs translation from logical addresses to physical addresses in the virtual memory. To achieve high-speed address translation, the MMU generally uses a translation look-aside buffer (hereinafter referred to as a TLB). The TLB functions as a cache of a page table stored in a storage unit and includes entries that associate logical addresses and physical addresses of the individual pages of storage areas divided by the MMU. The MMU translates the logical address of a target page accessed by the program to a physical address on the basis of an entry in the TLB.
Since the TLB is a buffer installed in a processor, it can be accessed at high speed but has small data storage capacity. The TLB can therefore include merely a limited number of entries. Meanwhile, a technology for improving the performance of a processor by increasing the number of threads that can be executed simultaneously on a processor has recently been advancing. Therefore, the number of TLB entries needs to be increased with an increase in the number of threads. However, since it is generally difficult to increase the number of TLB entries while keeping access latency, the number of TLB entries per thread decreases. This increases the frequency of TLB misses in which entries corresponding to the logical addresses of target pages accessed by individual threads are not present in the TLB, thus causing TLB thrashing.
As a solution to such a TLB miss, for example, the MMU reads an entry corresponding to a target logical address from a page table. However, the page table is generally stored in a storage unit outside the processor. Therefore, much time is required to read the entry from the page table.